1. Technical Field
This invention relates to a phase-locked loop (PLL) circuit, as well as a PLL frequency synthesizer and a radio receiver that use the PLL circuit. More particularly, the invention relates to a PLL frequency synthesizer that is driven on low voltage, that does not use any active filter in the PLL and that still is capable of rapid frequency locking as soon as the current frequency of PLL oscillation shifts to a different value.
2. Background Art
The PLL frequency synthesizes is used as part of a circuit that supplies the output of a PLL circuit to a local oscillator in a radio receiver or a modulating circuit in a radio transmitter and which converts the input signal to a signal of a given frequency which may be an intermediate frequency in the case of the radio receiver. In the PLL frequency synthesizer, the cutoff frequency of the low-pass filter (LPF) which is inserted into the loop of a PLL circuit is related not only to the locking range over which frequencies can be locked by the PLL but also to the response characteristics for the case of a shift in the frequency range, say, from the AM to FM range. Hence, the cutoff frequency of the LPF in the PLL is selected in accordance with the broadcasting station at which the frequency controls have been tuned in. If the frequency channel is changed to a certain station, tracking of the frequency of the signals from that station must be accomplished automatically and as rapidly as possible. To meet this need, the indicial response characteristics in the case where the cutoff frequency of the LPF in the PLL is changed to a different value must also be considered. Generally speaking, the locking range of the PLL becomes narrow as the cutoff frequency of the LPF decreases with respect to the input signal and vice versa.
One of the approaches that have dealt with these problems of the PLL circuit is described in Unexamined Published Japanese Utility Model Application (kokai) Hei 1-65528. A prior art technology that is relevant to the present invention is a circuit that uses a lead-lag filter in the PLL and which is described in "Wakaru PLL no Oyo Tekunikku (Applied Techniques of the PLL Circuit)", ed. by S. Takamatsu, published by Nihon Hoso Shuppankyokai, Jan. 20, 1988.
FIG. 3 shows a prior art PLL frequency synthesizer of the type contemplated by the invention which produces local oscillations in the frequency range from the AM to FM band. The heart of this synthesizer is to change the damping resistance in response to a frequency shift in such a way as to accomplish rapid locking to the selected frequency.
Referring to FIG. 3, numeral 10 designates the PLL frequency synthesizer and numeral 11 is a voltage-controlled oscillating circuit (VCO) containing a varactor diode 11a, the capacitance of which varies in response to the terminal voltage so as to control the frequency of oscillation. Shown by numeral 12 is an integrated phase comparator circuit for PLL control (hereunder abbreviated as "PLL IC") with a built-in programmable divider; numeral 13 is a microprocessor unit (MPU); numeral 14 is a quartz or ceramic oscillator; numeral 15 is an active filter capable of changing the damping time constant; numeral 16 is an integrating circuit composed of a resistor Ri and a capacitor Ci; numeral 17 is the receiving antenna on a radio receiver; numeral 18 is a radio-frequency (RF) amplifier for amplifying the received signal at frequencies in the RF range; and numeral 19 is a mixing circuit for converting the amplified signal to one having an intermediate frequency. In the system shown in FIG. 3, the active filter 15 and the integrating circuit 16 serve as an amplifier and a two-stage LPF in the PLL to change the cutoff frequency or damping characteristics so that the VCO will oscillate with good response at frequencies ranging from the AM to FM band.
PLL IC 12 contains a shaping circuit 21 that receives the output of VCO 11 and shapes its waveform to a pulse signal, a reference frequency oscillating circuit 23, a phase comparator circuit (PC) 24, a charge/discharge pulse generator circuit (charge pumping circuit) 25, and a switching circuit 26. The programmable divider 22 is composed of a programmable counter that counts the number of output pulses from the shaping circuit 21. The reference frequency oscillating circuit 23 is connected to the quartz oscillator 14 and generates a reference clock in accordance with the center frequency of the oscillation by 14. The phase comparator circuit 24 compares the phase of the output from the reference frequency oscillating circuit 23 with that of the output from the programmable divider 22 and produces the output of the comparison and its inverted output. The charge pumping circuit 25 receives pulse signals indicative of these two outputs and supplies the active filter 15 with charging/discharging pulses. The switching circuit 26 receives the signal from the microprocessor unit 13 and turns on and off to change the damping time constant.
The active filter 15 is composed of a resistor R connected to a supply line Vcc, as well as an n-type field-effect transistor (FET) Q, damping resistors R1 and R2 that are connected to the input of transistor Q, and a series feedback circuit that is composed of a resistor R3 and a capacitor C and which acts as a loop filter that feeds the output of transistor Q back to its input.
The PLL frequency synthesizer shown in FIG. 3 operates as follows. In response to an applied frequency selection signal SEL, MPU 13 generates dividing data n and a control signal CS in accordance with the selected frequency. In accordance with the operator-selected frequency, the programmable divider 22 receives the signal of the dividing data n from the MPU 13 and counts n output pulses from the VCO 11, whereupon pulses whose frequency is one nth of the input frequency are generated. As a result, those pulses which have been frequency-divided by n in accordance with the dividing data n are sent out to the phase comparator circuit 24.
The phase comparator circuit 24 compares the phase of the frequency-divided pulses with that of the clock signal having the reference frequency. The pulses that result from the comparison and their inverted pulses are then supplied to the charge pumping circuit 25, which supplies the active filter 15 with ON/OFF pulses of a width that complies with the width of the pulses from the phase comparator circuit 24. As a result, the component of ON/OFF pulses below the cutoff frequency of the active filter 15 is transmitted by the latter and sent out to the integrating circuit 16. The capacitor Ci in the integrating circuit 16 is then supplied with a voltage signal to be applied to the varactor diode 11a. This voltage signal controls the frequency of oscillation of VCO 11 in such a way that the divided frequency that has been produced from the programmable divider 22 is locked to the reference frequency from the reference frequency oscillating circuit 23, whereupon the frequency of oscillation of VCO 11 is locked to a value that is a multiple as determined by the dividing data n. Thus, the frequency of oscillation of VCO 11 can be set in accordance with the dividing data n received by the programmable divider 22.
Suppose here the case of selecting an FM frequency, in which the frequency of oscillation of the VCO 11 is on the order of megahertz. Since the center frequency of PLL oscillation shifts to a different region as a result of the change from the AM to FM band, high-speed frequency locking cannot be accomplished unless the damping factor of indicial response is reduced to a sufficiently low level. To meet this need, a large value of the damping resistance is selected for the FM range and the output of the charge pumping circuit 25 is supplied to the active filter 15 via the resistor R1. Consider next the case of selecting an AM frequency, in which the frequency of oscillation of VCO 11 is on the order of kilohertz. To achieve rapid frequency locking, the damping factor of PLL indicial response must be increased (namely, the damping resistance must be reduced). To meet this need, the output of the charge pumping circuit 25 is supplied to the active filter 15 via a circuit in which resistor R1 of the greater value is connected parallel to resistor R2 of the smaller value. Hence, if an AM frequency is selected, the switching circuit 26 turns on in response to control signal CS from the MPU 13 and the two resistors R1 and R2 are connected parallel to each other.
In FIG. 3, the active filter 15 is shown as a component externally connected to PLL IC 12. In most cases, however, the transistor portion of the active filter 15 and the associated peripheral circuit are internal parts of PLL IC 12 and other ICs. If the frequency of oscillation of the VCO is to be changed by controlling the voltage applied to the varactor diode, high voltage control is necessary and, hence, an active filter capable of amplification is used customarily.
In the case described above the charge pumping circuit 25 and the active filter 15 are included in the PLL. If all of these components are assembled in an IC, the efficiency of circuit integration is impaired by the inclusion of the active filter. If the active filter 15 is externally connected to the PLL IC, the number of circuit components is one too many. Further, the active filter is typically provided with a bias voltage from the supply line via the resistor and, hence, the maximum voltage that controls the VCO is lower than the supply line voltage and the maximum voltage for oscillation control is easily limited. As a further problem, the current flowing from the charge pump 25 to the integrating circuit 16 via the active filter 15 will prolong the cycle time of capacitor Ci and the speed of tracking a selected frequency is slowed down. This problem is particularly serious in the case where the PLL circuit under discussion is applied to circuits of a type to be driven on low voltage. With circuits of the low-voltage drive type, the range of control voltage becomes narrow and the frequency control range is limited accordingly. As a result, the tracking efficiency of the PLL over a wide range of frequencies from the AM to FM band is reduced and the range of frequencies that can be tracked becomes accordingly narrow.